V.V. Sapozhnikov, Vl.V. Sapozhnikov, D.V. Efanov, M.R. Cherepanova
Èlektron. model. 2018, 38(2):27-48
The analysis of modulo codes with summation of active bits properties in concurrent error detection systems for the data vector length change was performed. Dependence of errors of different types on different values of modulo, that are connected with the number of bits in data vectors and their calculation rules were determined. It was shown that modulo codes with summation do not detect the same rate of given multiplicity d errors for any data vector length without reference to modulo. It is shown in experiments that reduction of modulo value for real logic circuits does not result in the increase of the number of undetectable errors on its outputs in many cases.
concurrent error detection system, hardware redundancy, code with summation, Berger code, parity code,modulo code with summation, detection of errors in combinational circuits.
1. Parkhomenko, P.P. and Sogomonyan, E.S. (1981), Osnovy tekhnicheskoy diagnostiki (optimizatsiya algoritmov diagnostirovaniya, apparaturnye sredstva) [Basics of technical diagnostics (optimization of diagnostic algorithms and equipment)], Energoatomizdat, Moscow, Russia.
2. McCluskey, E.J. (1986), Design logic principles: with emphasis on testable demicustom circuits, Prentice Hall PTR, New Jersey, USA.
3. Goessel, M. and Graf, S. (1994), Error detection circuits, McGraw-Hill, London, UK.
4. Drozd, A.V.,Kharchenko, V.S.,Antoshchuk, S.G., and et al. (2012), Rabochee diagnostirovanie bezopasnykh informatsionno-upravlyayuschikh sistem [On-line testing for safe instrumentation and control systems], National Aerospace University «KhAI», Kharkov, Ukraine.
5. Touba, N.A. and McCluskey, E.J. (1997), “Logic synthesis of multilevel circuits with concurrent error detection”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, pp. 783-789.
6. Nicolaidis, M. and Zorian, Y. (1998), “On-line testing for VLSI – A compendium of approaches”, Journal of Electronic Testing: Theory and Applications, no. 12, pp. 7-20.
7. Mitra, S. and McClaskey, E.J. (2000), “Which concurrent error detection scheme to choose?”, Proceedings of International Test Conference, Atlantic City, NJ, USA, October 3-5, 2000, pp. 985-994.
8. Drozd, A.V. (2008), “Untraditional view on operational diagnostics of computing devices”, Control sciences, no. 2, pp. 48-56.
9. Slabakov, E.V. and Sogomonyan, E.S. (1981), “Self-checking computing devices and systems (review)”, Avtomatika i telemekhanika, no. 11, pp. 147-167.
10. Rao, T.R. and Fujiwara, E. (1989), Error control coding for computer systems, Prentice Hall, New York, USA.
11. Sogomonyan, E.S. and Slabakov, E.V. (1989), Samoproveryaemye ustroystva i otkazoustoychivye sistemy [Self-checking devices and failover systems], Radio i svyaz, Moscow, Russia.
12. Fujiwara, E. (2006), Code design for dependable systems: Theory and practical applications, John Wiley & Sons, New Jersey, USA.
13. Lala, P.K. (2007), Principles of modern digital design, John Wiley & Sons, New Jersey, USA.
14. Jha, N.K. (1991), “Totally self-checking checker designs for Bose-Lin, Bose and Blaum Codes”, IEEE Trans. Computer-Aided Design, Vol. CAD-10, pp.136-143.
15. Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (1992), Samoproveryaemye diskretnye ustroystva [Self-checking digital devices], Energoatomizdat, St. Petersburg, Russia.
16. Bose, B. and Lin, D.J. (1985), “Systematic unidirectional error-detection codes”, IEEE Trans. Comput., Vol. C-34, pp. 1026-1032.
17. Das, D. and Touba, N.A. (1999), “Synthesis of circuits with low-cost concurrent error detection based on Bose-Lin codes”, Journal of Electronic Testing: Theory and Applications, Vol. 15, Iss. 1-2, pp. 145-155.
18. Piestrak, S.J. (1995), Design of self-testing checkers for unidirectional error detecting codes, Oficyna Wydawnicza Politechniki Wrocavskiej, Wrocaw, Poland.
19. Aksyonova, G.P. (1979), “Necessary and sufficient conditions for the design of totally checking circuits of compression by modulo 2”, Avtomatika i telemekhanika, no. 9, pp. 126-135.
20. Ghosh, S., Basu, S. and Touba, N.A. (2005), “Synthesis of low power CED circuits based on parity codes”, Proceedings of 23rd IEEE VLSI Test Symposium (VTS’05), Palm Springs, California, USA, May 1-5, 2005, pp. 315-320.
21. Aksyonova, G.P. (2008), “On functional diagnosis of discrete devices under imperfect data processing conditions”, Problemy upravleniya, no. 5, pp. 62-66.
22. Berger, J.M. (1961), “A note on error detecting codes for asymmetric channels”, Information and Control, Vol. 4, Iss. 1, pp. 68-73.
23. Sapozhnikov, V., Sapozhnikov, Vl. and Efanov, D. (2015), “Modular Sum Code in Building Testable Discrete Systems”, Proceedings of 13th IEEE East-West Design&Test Symposium (EWDTS'2015), Batumi, Georgia, September 26-29, 2015, pp. 181-187.
24. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2015), “Application of sum codes for synthesis of railway automation and remote control systems using programmable logic integrated circuits”, Avtomatika na transporte, Vol. 1, no. 1, pp. 84-107.
25. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2015), “Errors classification in information vectors of systematic codes”, Izvestiya Vysshikh Uchebnykh Zavedeniy. Priborostroenie, Vol. 58, no. 5, pp. 333-343.
26. Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2010), “On sum code properties in concurrent error detection systems", Avtomatika i telemekhanika, no. 6, pp. 155-162.
27. Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2015), “Applications of modular summation codes to concurrent error detection systems for combinational Boolean circuits”, Avtomatika i telemekhanika, no. 10, pp. 152-169.
28. Collection of digital design Benchmarks, available at: http://ddd.fit.cvut.cz/prj/Benchmarks/.
29. Sapozhnikov, V., Sapozhnikov, Vl., Efanov, D. and Blyudov, A. (2014), “On the synthesis of unidirectional combinational circuits detecting all single faults”, Proceedings of the 12th IEEE East-West Design & Test Symposium (EWDTS'2014), Kyiv, Ukraine, September 26-29, 2014, pp. 116-125.