V.V. Sapozhnikov, Vl.V. Sapozhnikov, D.V. Efanov, M.R. Cherepanova
Èlektron. model. 2018, 38(2):27-48
https://doi.org/10.15407/emodel.38.02.027
ABSTRACT
The analysis of modulo codes with summation of active bits properties in concurrent error detection systems for the data vector length change was performed. Dependence of errors of different types on different values of modulo, that are connected with the number of bits in data vectors and their calculation rules were determined. It was shown that modulo codes with summation do not detect the same rate of given multiplicity d errors for any data vector length without reference to modulo. It is shown in experiments that reduction of modulo value for real logic circuits does not result in the increase of the number of undetectable errors on its outputs in many cases.
KEYWORDS
concurrent error detection system, hardware redundancy, code with summation, Berger code, parity code,modulo code with summation, detection of errors in combinational circuits.
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