MODULO CODES WITH SUMMATION IN CONCURRENT ERROR DETECTION SYSTEMS. II. DECREASE OF HARDWARE REDUNDANCY OF CONCURRENT ERROR DETECTION SYSTEMS

V.V. Sapozhnikov, Vl.V. Sapozhnikov, D.V. Efanov, M.R. Cherepanova

Èlektron. model. 2018, 38(3):47-62
https://doi.org/10.15407/emodel.38.03.047

ABSTRACT

Ways of concurrent error detection systems organization are described. Influence of code with summation modulo value on the concurrent error detection system hardware redundancy is studied. Classification of modulo codes with summation is offered.

KEYWORDS

concurrent error detection system, hardware redundancy, code with summation, Berger code, parity code, modulo codes with summation, detection of error in combinational circuits.

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