D.V. Efanov, D. Sc. (Tech.)
Federal State Autonomous Educational Institution of Higher Education
“Russian University of Transport”
Russian Federation, 127994, Moscow, Obraztsova str., build. 9/9
A method for constructing a family of sum codes is described based on weighting the transitions between groups of bits in the data vector. In this case, weights are used that are powers of the number 2. This makes it possible to obtain a code with check bits described by linear functions. The proposed weight-based sum code makes it possible to synthesize self-checking devices based on the standard elements and optimization methods of the logical device’s structures. A standard structure of a device with a concurrent error-detection (CED) circuit based on transitions weight-based sum codes between bits groups in the data vector is presented. The standard structure advantage lies in the possibility of synthesizing CED circuits with technical implementation reduced complexity by using codes with check bits numbers that are much smaller than the data bits numbers. Self-checking devices synthesized using the described codes in some cases may turn out to be less redundant than when using the standard duplication structure. The structure disadvantage is the need to consider the restrictions on the multiplicity of errors arising at the outputs of the diagnostic objects. This limitation increases with a decrease in the number of check bits. Despite this, in many cases, the use of a standard structure based on transitions weight-based sum code between groups of digits in the data vector makes it possible to synthesize self-checking digital devices. Using a standard structure for organizing a CED circuit allows going to implement of fault-tolerant digital devices according to standard structures, one of which is given in this article.
self-checking built-in control circuit, checking of calculations, transitions weight-based sum code, detection of errors in the data vector, standard CED circuit structure, standard fault-tolerant device structure.
- Matrosova, A.Yu. (1990), Algoritmicheskie metody sinteza testov [Algorithmic methods for the synthesis of tests], Publishing house of Tomsk University, Tomsk, USSR.
- Wang, L.-T., Wu, C.-W. and Wen, X. (2006), VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann Publishers, San Francisco, USA.
- Göessel, M., Ocheretny, V., Sogomonyan, E. and Marienfeld, D. (2008), New Methods of Concurrent Checking: Edition 1, Springer Science+Business Media B.V., Dordrecht, Netherlands.
- Navabi, Z. (2011), Digital System Test and Testable Design: Using HDL Models and Architectures, Springer Science+Business Media.
- Drozd, A.V., Kharchenko, V.S. and Antoshchuk, S.G. (2012), Rabochee diagnostirovanie bezopasnykh informatsionno-upravljayustchikh sistem [Objects and Methods of On-Line Testing for Safe Instrumentation and Control Systems], National Aerospace University "KhAI", Kharkov, Ukraine.
- Hahanov, V. (2018), Cyber Physical Computing for IoT-driven Services, Springer International Publishing AG, New York, USA,
- Mikoni, S.V., Sokolov, B.V. and Yusupov, R.M. (2018), Kvalimetriya modelej i polimodel'nyh kompleksov [Qualimetry of models and polymodel complexes], Academy of Science, Moscow, Russia.
- Sogomonyan, E.S. and Slabakov, E.V. (1989), Samoproverjaemyje ustrojstva i otkazoustojchivyje sistemy [Self-checking devices and failover systems], Radio i Svjaz, Moscow, USSR.
- Mikoni, S.V. (1992), Obshchie diagnosticheskie bazy znanij vychislitel'nyh sistem [General Diagnostic Knowledge Base of Computing Systems], SPIIRAN, St. Petersburg, Russia.
- Parkhomenko, P.P. and Sogomonyan, E.S. (1981), Osnovy tekhnicheskoj diagnostiki (optimizatsija algoritmov diagnostirovanija, apparaturnyje sredstva) [Basics of technical diagnostics (optimization of diagnostic algorithms and equipment)], Energoatomizdat, Moscow, USSR.
- Goessel, M. and Graf, S. (1994), Error Detection Circuits, McGraw-Hill, London, UK.
- Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2019), Osnovy teorii nadezhnosti i tekhnicheskoj diagnostiki [Fundamentals of the theory of reliability and technical diagnostics], Publishing House "Lan", St. Petersburg, Russia.
- Nicolaidis, M, and Zorian, Y. (1998), “On-Line Testing for VLSI – А Compendium of Approaches”, Journal of Electronic Testing: Theory and Application, Vol. 12, no. 1-2, pp. 7-20,
- Mitra, S. and McCluskey, E.J. (2000), “Which Concurrent Error Detection Scheme to Сhoose?”, Proceedings of International Test Conference, Atlantic City, NJ, USA, October 03-05, 2000, pp. 985-994.
- Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2018), Kody Khemminga v sistemakh funktsionalnogo kontrolja [Hamming Сodes in Concurrent Error Detection Systems of Logic Devices], Nauka, St. Petersburg, Russia.
- Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2020), Kody s summirovaniem dlya sistem tekhnicheskogo diagnostirovaniya. Tom 1: Klassicheskie kody Bergera i ih modifikacii [Sum Codes for Technical Diagnostics Systems. Volume 1: Classical Berger Codes and Their Modifications], Nauka, Moscow, Russia.
- Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2021), Kody s summirovaniem dlya sistem tekhnicheskogo diagnostirovaniya. Tom 2: Vzveshennyje kody s summirovanijem [Sum Codes for Technical Diagnostics Systems. Volume 2: Weight-Based Sum Codes], Nauka, Moscow, Russia.
- Aksjonova, G.P. (1973), “Method of Synthesizing Built-in Monitoring Arrangements for Automata with Memory”, Avtomatika i telemekhanika, 1973, 34, no. 2, pp. 267-273.
- Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V. and Dmitriev, V.V. (2017), “New Structures of the Concurrent Error Detection Systems for Logic Circuits”, Avtomatika i telemekhanika, Vol. 78, no. 2, pp. 300-312,
- Saposhnikov, V. and Saposhnikov, Vl. (1999), “New Code for Fault Detection in Logic Circuits”, Trudy 4-y konferentsii po netraditsionnym elektromekhanicheskim i elektricheskim sistemam [Proceedings of 4th International Conference on Unconventional Electromechanical and Electrical Systems], St. Petersburg, Russia, June 21-24, 1999, pp. 693-696.
- Nikolos, D. (1998), “Self-Testing Embedded Two-Rail Checkers”, On-Line Testing for VLSI, Ch. 7, pp. 69-79,
- Lala, P.K. (2001), Self-Checking and Fault-Tolerant Digital Design, Morgan Kaufmann Publishers, San Francisco, USA.
- Zakrevskij, A., Pottosin, Yu. and Cheremisinova, L. (2009), Optimization in Boolean Space, TUT Press, Tallinn, Estonia.
- Sentovich, E.M., Singh, K.J., Moon, C., Savoj, H., Brayton, R.K. and Sangiovanni-Vincentelli, A. (1992), “Sequential Circuit Design Using Synthesis and Optimization”, Proceedings IEEE International Conference on Computer Design: VLSI in Computers & Processors, October 11-14, 1992, Cambridge, MA, USA, pp. 328-333, DOI: 1109/ ICCD.1992.276282.
- Sentovich, E. M., Singh, K. J., Lavagno L. et al (1992), SIS: A System for Sequential Circuit Synthesis, Electronics Research Laboratory, Department of Electrical Engineering and Computer Science, University of California, Berkeley, USA.
- Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2020), “Signal Correction Circuit for Combinational Automation Devices on the Basis of Boolean Complement with Control of Calculations by Parity”, Informatica, Vol. 17, no. 2, pp. 71-85, available at:
- Sapozhnikov, V., Sapozhnikov, Vl. and Efanov, D. (2020), “Typical Signal Correction Structures Based on Duplication with the Integrated Control Circuit”, Proceedings of 18th IEEE East-West Design & Test Symposium (EWDTS’2020), Varna, Bulgaria, September 4-7, 2020, pp. 78-87, DOI: 1109/EWDTS50664.2020.9224649.
- Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2020), “Typical Structure of a Duplicate Error Correction Scheme with Code Control with Summation of Weighted Transitions”, Elektronne modelyuvannya, Vol. 42, no. 5, рp. 38-50,
- Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2021), “Boolean-Complement Based Fault-Tolerant Electronic Device Architectures”, Avtomatika i telemekhanika, Vol. 82, no. 8, pp. 1403-1417,