Microprocessor Based on the Minimal Hardware Principle

V.K. Dobrovolskyi, Ph.D., independent CPU architect
(Kyiv, Ukraine, тел. (+38) 0982798517; e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.)

Èlektron. model. 2019, 41(6):77-90


A project of the new RISC microprocessor architecture is proposed on the basis of the minimal hardware principle (the MHP RISC processor) targeted on effective parallelization. The notion of instruction group is postulated which is formed by the smart compiler. The header instruc-tion of the group points out how many instructions should be issued in parallel. The concept of the flux as a composite of instruction stream and data flow, supported by certain flux hardware, and used for parallelization on higher levels is developed. Formats of typical instructions and their usage are explained on examples. A new method for the loop control which is applicable to loops with the increasing/decreasing numeric loop variable, and also, a new method for the branch parallelization are proposed. The proposed architecture does not contain simultaneous multithreading, register renaming, instruction reordering, out-of-order execution, speculative execution, superscalar execution, delayed branch, branch prediction which all require much hardware. These all are substituted by the notion of instruction group, concept of flux, special instructions, and strong compiler support.


microprocessor, parallelism, comparisons, loop control, branch parallelization.


1. Dumas II, J.D. (2017), Computer Architecture. Fundamentals and Principles of Computer Design, Taylor & Francis Group.
2. Stallings, W. (2013), Computer Organization and Architecture. Designing for Perfor-mance, Ninth edition, Pearson Education.
3. Patterson, D.A. and Hennessy, J.L. (2009), Computer Organization and Design. The Hardware/ Software Interface. Fourth edition, Morgan Kaufmann Publishers.
4. Melnyk, A.O. (2008), Architecture of Computer. Manual, Lutsk regional printing, Ukraine.
5. Sima, D., Fountain, T.J. and Kacsuk, P. (1997), Advanced Computer Architectures: A De-sign Space Approach, Addison-Wesley.
6. Tremblay, M., Chan, J., Conigliaro, S.W. and Tse, S.S. (2000), “The MAJC Architecture: A Synthesis of Parallelism and Scalability”, IEEE MACRO, November-December, pp. 12-25.
7. Dobrovolskyi, V.K. (2018), “Microprocessor with Explicit Parallelism’’, the Proceedings of SIMULATION-2018, September 12-14, 2018, Kyiv, Ukraine, pp. 135-138. ISBN 978-966-02-8587-3
8. Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L. and Tullsen, D.M. (1997), “Simultaneous Multithreading: A Platform for Next-Generation Processors” IEEE Micro, pp. 12-19.
9. Lo, J., Eggers, S., Emer, J., Levy, H., Stamm, R. and Tullsen, D. (1997), “Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multi-threading”, ACM Transactions on Computer Systems, pp. 322-354.

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