Vector-deductive Memory-based Transactions for Fault-as-address Simulation

W. Gharibi 1, PhD, Prof., A. Hahanova 2, Cand. T. Sc, Ass. Prof.,
V. Hahanov 2, D.Sc., Prof., S. Chumachenko 2, D.Sc., Prof.,
E. Litvinova 2, D.Sc., Prof., I. Hahanov 2

1 The University of Missouri-Kansas City, MO 64110 USA,
  This email address is being protected from spambots. You need JavaScript enabled to view it.
2 Kharkiv National University of Radio Electronics,
  Ukraine, 61166, Kharkiv, Nauka Avenue, 14,
  (057) 7021 326, This email address is being protected from spambots. You need JavaScript enabled to view it.

Èlektron. model. 2023, 45(1):03-26


The main idea is to create logic-free vector computing, using only read-write transactions on address memory. The strategic goal is to create a deterministic vector-quantum computing using photons for read-write transactions on stable subatomic memory elements. The main task is to implement new vector computing models and methods based on primitive read-write transactions in vector flexible interpretive fault modeling and simulation technology, where data is used as addresses for processing the data itself. The essence of vector computing is read-write transactions on vector data structures in address memory. Vector computing is a computational process based on elementary read-write transactions over cells of binary vectors that are stored in address memory and form a functionality where the input data to be processed is the addresses of these cells. The advantages of a vector universal model for a compact description of ordered processes, phenomena, functions, and structures are defined for the purpose of their parallel analysis. Analytical expressions of logic, which require algorithmically complex calculators, are replaced by output state vectors of elements and digital circuits, focused on the parallelism of register logical procedures on regular data structures. A vector-deductive method for formula synthesis for propagating input lists (data) of faults is proposed, which has a quadratic computational complexity of register operations. A new matrix of deductive vectors has been synthesized, which is characterized by the following properties: compactness, parallel data processing based on a single read-write transaction in memory, elimination of traditional logic from fault simulation procedures, full automation of its synthesis process, and focus on technological solving all problems of technical diagnosis. In the work, the transition to vector logic in the organization of computing and the elimination of traditional logic presented in the form of tables and analytical expressions were carried out. The use of read-write transactions on memory in the absence of a command system focuses the new vector-logic computing towards deterministic quantum architectures based on stable subatomic memory particles.


vector computing, vector form of logic, matrix of deductive vectors, table of synthesis of deductive vectors, analytical form of structures, deductive-vector method of fault analysis, digital circuit, vector model of defects, functions and structures, sequencer of vector deductive fault simulation.


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