THE RESEARCH OF TWO-MODULUS CODES WITH SUMMATION OF UNIT BITS WITH CALCULATION BY MODULO “FOUR”

D.V. Efanov, Cand. Sc. (Eng.)
Russion Transport University (MITE), 9 Obraztsov St, Moscow, 127994, Russian Federation, e-mail: efanov@ieee.org),
V.V. Sapozhnikov, Dr Sc. (Eng.),  Vl. V. Sapozhnikov,  Dr Sc. (Eng.),, V.A. Schagina
Emperor Alexander I St.Petersburg State Transport University, 9 Moskovsky Ave, Saint Petersburg, 190031, Russian Federation, e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.)

Èlektron. model. 2018, 40(4):29-54
https://doi.org/10.15407/emodel.40.04.029

ABSTRACT

The methods of codes with summation of unit bits construction are analyzed. In addition to the classical sum code (Berger code), there is a family of modified codes, which are built through the allocation of controlled subsets of data vector’s bits. The connection between the methods of the classical Berger code modification is determined and new two-module codes with summation of unit data bits are proposed. The methods of two-module sum codes construction are also analyzed; their features and characteristics are described. The general block diagram of two-module sum code generators is presented.

KEYWORDS

technical diagnostics, sum code, modified Berger code, two-module sum code, undetectable error.

REFERENCES

  1. Sapozhnikov, V., Sapozhnikov, Vl.V., Khristov, H.A. and Gavzov, D.V. (1995), Metody postroeniya bezopasnyh mikroehlektronnyh sistem zheleznodorozhnoi avtomatiki [Methods for constructing safety microelectronic systems for railway automation], Ed. Vl.V. Sapozh- nikov, Transport, Moscow, Russia.
  2. Pradhan, K. (1996), Fault-tolerant computer system design, Prentice Hall, New York, USA.
  3. Fujiwara, E. (2006), Code design for dependable systems: Theory and practical applications, John Wiley & Sons, New Jersey, USA. https://doi.org/10.1002/0471792748
  4. Göessel, , Ocheretny, V., Sogomonyan, E. and Marienfeld, D. (2008), New methods of con- current checking, Edition 1, Springer Science+Business Media B.V., Dodrecht, Netherlands.
  5. Ubar, , Raik, J. and Vierhaus, H.-T. (2011), Design and test technology for dependable systems-on-chip (Premier Reference Source), Information Science Reference, IGI Global, Hershey-New York, USA.
  6. Lisenkov, M., Bestemyanov, P.F., Leushin, V.B., et al. (2009), Sistemy upravleniya dvizheniem poezdov na peregonakhUchebnik dlya VUZov Zh.-d. Transporta, Chast. 2, 3 [Traffic control systems on the trains: Manual for Inst. of Railway Transport, part 2, 3], Ed. 

    V.M. Lisenkov, Uchebno-metodicheskiy tsentr po obrazovaniyu na zheleznodorozhnom transporte, Moscow, Russia. 

    Problemy upravleniya,  no. 2, pp. 48-56. [Self-checking discrete devices], Energoatomizdat, St. Petersburg, Russia.
  7. Tshagharyan, , Harutyunyan, G., Shoukourian, S. and Zorian, Y. (2017), Experimental study on Hamming and Hsiao codes in the context of embedded applications, Proceedings of the 15th IEEE East-West Design & Test Symposium (EWDTS`2017), Novi Sad, Serbia, Sept. 29-Oct. 2, 2017, pp. 25-28. DOI: 10.1109/EWDTS.2017.8110065. https://doi.org/10.1109/EWDTS.2017.8110065
  8. Parkhomenko, P. and Sogomonyan, E.S. (1981), Osnovy tekhnicheskoi diagnostiki (opti- mizatsiya algoritmov diagnostirovaniya, apparaturnyie sredstva) [Basics of technical diag- nostics (optimization of diagnostic algorithms and equipment)], Energoatomizdat, Moscow, USSR.
  9. McCluskey, J. (1986), Logic design principles: With emphasis on testable semicustom cir- cuits, Prentice Hall PTR, New Jersey, USA.
  10. Sogomonyan, S. and Slabakov, E.V. (1989), Samoproveryaemye ustroistva i otkazous- toichivye sistemy [Self-checking devices and failover systems], Radio i svyaz, Moscow, USSR.
  11. Nicolaidis, and Zorian, Y. (1998), On-Line Testing for VLSI – À Compendium of Ap- proaches, Journal of Electronic Testing: Theory and Applications, no. 12, pp. 7-20. DOI: 10.1023/A:1008244815697. https://doi.org/10.1023/A:1008244815697
  12. Matrosova, Yu., Levin, I. and Ostanin, S.A. (2000), Self-checking synchronous FSM net- work design with low overhead, VLSI Design, Vol. 11, Iss. 1, pp. 47-58. DOI: 10.1155/ 2000/46578.
  13. Mitra, and McCluskey, E.J. (2000), Which concurrent error detection scheme to choose?, Proceedings of International Test Conference, USA, Atlantic City, NJ, October 03-05, 2000, pp. 985-994. DOI: 10.1109/TEST.2000.894311. https://doi.org/10.1109/TEST.2000.894311
  14. Kubalik, and Kubatova, H. (2005), Parity codes used for on-line testing in FPGA, Acta Polytechnika, Vol. 45, no. 6, pp. 53-59.
  15. Drozd, V., Kharchenko, V.S., Antoschuk, S.G., et al. (2012), Rabochee diagnostirovanie bezopasnykh informatsionno-upravlyayuschikh sistem [On-line testing for safe instrumenta- tion and control systems], Natsionalny Aerokosmicheskiy Universitet «KhAI», Kharkov, Ukraine.
  16. Kharchenko, , Kondratenko, Yu. and Kacprzyk, J. (2017), Green IT engineering: Con- cepts, models, complex systems architectures, Springer Book Series Studies in Systems, De- cision and Control, Vol. 74. DOI 10.1007/978-3-319-44162-7.
  17. Hamming, W. (1986), Coding and information theory: 2 Sub-edition, Prentice-Hall, New York, USA.
  18. Lala, K. (2007), Principles of modern digital design, John Wiley & Sons, New Jersey, USA. https://doi.org/10.1002/0470125217
  19. Drozd, V. (2008), “Untraditional view on operational diagnostics of computing devices”
  20. Sapozhnikov, V., and Sapozhnikov, Vl.V. (1992), Samoproveryaemye diskretnye ustroistva 

    Theory and Applications, Vol. 12, Iss. 1-2, pp. 41-53. DOI: 10.1023/A:1008257118423. https://doi.org/10.1023/A:1008257118423

  21. Piestrak, J. (1995), Design of self-testing checkers for unidirectional error detecting codes, Oficyna Wydawnicza Politechniki Wroclavskiej, Wrolcaw, Poland.
  22. Efanov, , Sapozhnikov, V. and Sapozhnikov, Vl. (2017), Generalized algorithm of build- ing summation codes for the tasks of technical diagnostics of discrete systems, Proceedings of the 15th IEEE East-West Design & Test Symposium (EWDTS`2017), Novi Sad, Serbia, Sept. 29-Oct. 2, 2017, pp. 365-371. DOI: 10.1109/EWDTS.2017.8110126. https://doi.org/10.1109/EWDTS.2017.8110126
  23. Berger, J.M. (1961), A note on error detection codes for asymmetric channels, Information and Control, 4, Iss. 1, pp. 68-73. DOI: 10.1016/S0019-9958(61)80037-5. https://doi.org/10.1016/S0019-9958(61)80037-5
  24. Efanov, V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2010), “On sum code properties in concurrent error detection systems”, Avtomatika i telemekhanika, no. 6, pp. 155-162.
  25. Sapozhnikov, V., Sapozhnikov, Vl.V. and Efanov, D.V. (2015), “Errors classification in information vectors of systematic codes”, Izvestiya Vysshikh Uchebnykh ZavedeniyPribo- rostroenie, Vol. 58, no. 5, pp. 333-343. DOI 10.17586/0021-3454-2015-58-5-333-343. https://doi.org/10.17586/0021-3454-2015-58-5-333-343
  26. Morosow, , Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Göessel, M. (1998), Self-check- ing combinational circuits with unidirectionally independent outputs, VLSI Design, Vol. 5, Iss. 4, pp. 333-345. DOI: 10.1155/1998/20389. https://doi.org/10.1155/1998/20389
  27. Saposhnikov, V., Morosov, A., Saposhnikov, Vl.V. and Göessel M. (1998), A new design method for self-checking unidirectional combinational circuits, Journal of Electronic Testing:
  28. Ostanin, (2017), Self-checking synchronous FSM network design for path delay faults, Proceedings of the 15th IEEE East-West Design & Test Symposium (EWDTS`2017), Novi Sad, Serbia, Sept. 29-Oct. 2, 2017, pp. 696-699. DOI: 10.1109/EWDTS.2017.8110129. https://doi.org/10.1109/EWDTS.2017.8110129
  29. Efanov, V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2017), “Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger`s code”, Avtomatika i telemekhanika, no. 5, pp. 152-165. https://doi.org/10.1134/S0005117917050113
  30. Blyudov, , Efanov, D., Sapozhnikov, V. and Sapozhnikov, Vl. (2012), Properties of code with summation for logical circuit test organization, Proceedings of the 10th IEEE East- West Design & Test Symposium (EWDTS`2012), Kharkov, Ukraine, September 14-17, 2012, pp. 114-117. DOI: 10.1109/EWDTS.2013.6673150. https://doi.org/10.1109/EWDTS.2013.6673150
  31. Blyudov, A., Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2012), “Forma- tion of the Berger modified code with the minimum number of undetectable errors of data bits”, Electronnoe modelirovanie, Vol. 34, no. 6, pp. 17-29. 
  32. Efanov, , Sapozhnikov, V., Sapozhnikov, Vl. and Blyudov, A. (2013), On the problem of selection of code with summation for combinational circuit test organization, Proceedings of the 11th IEEE East-West Design & Test Symposium (EWDTS`2013), Rostov-on-Don, Rus- sia, September 27-30, 2013, pp. 261-266. DOI: 10.1109/EWDTS.2013.6673133. https://doi.org/10.1109/EWDTS.2013.6673133
  33. Blyudov, A., Efanov, D.V. Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2014), “On codes with summation of data bits in concurrent error detection systems”, Avtomatika i tele- mekhanika, no. 8, pp. 113-145. https://doi.org/10.1134/S0005117914080098
  34. Sapozhnikov, V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Effective method of modifying code with on-bits summation”, Izvestiya Vysshikh Uchebnykh Zavedeniy. Pribo- rostroenie, Vol. 60, no. 11, pp. 1020-1032. DOI: 10.17586/0021-3454-2017-60-11-1020-1032. https://doi.org/10.17586/0021-3454-2017-60-11-1020-1032
  35. Efanov, , Sapozhnikov, V. and Sapozhnikov, Vl. (2016), Generic two-modulus sum codes for technical diagnostics of discrete systems problems, Proceedings of the 14th IEEE East-West Design & Test Symposium (EWDTS`2016), Yerevan, Armenia, October 14-17, 2016, pp. 256-260. DOI: 10.1109/EWDTS.2016.7807713. https://doi.org/10.1109/EWDTS.2016.7807713
  36. Efanov, D., Sapozhnikov, V., Sapozhnikov, Vl. and Schagina, V. (2017), The analysis of two-modulus codes detection ability with summation of unit data bits compared to classical and modified Berger codes, Proceedings of the 15th IEEE East-West Design & Test Sympo- sium (EWDTS`2017), Novi Sad, Serbia, Sept. 29-Oct. 2, 2017, pp. 141-148. DOI: 10.1109/ EWDTS.2017.8110134. Izvestiya Vysshikh Uchebnykh Zavedeniy. Physics, Vol. 59, no. 8/2, pp. 33-36.
  37. Efanov, V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2018), Two-modulus codes with summation of one-data bits for technical diagnostics of discrete systems, Automatic Control and Computer Sciences, Vol. 52, Iss. 1, pp. 1-12. DOI: 10.3103/S0146411618010029. https://doi.org/10.3103/S0146411618010029
  38. Das, and Touba, N.A. (1999), Synthesis of circuits with low-cost concurrent error detection based on Bose-Lin codes, Journal of Electronic Testing: Theory and Applications, Vol. 15, Iss. 1-2, pp. 145-155. DOI: 10.1023/A:1008344603814. https://doi.org/10.1023/A:1008344603814
  39. Efanov, V. (2016), “The method of weighted code with summation generator synthesis”,

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