D.V. Efanov, V.V. Sapozhnikov, Vl.V. Sapozhnikov, D.V. Pivovarov

Èlektron. model. 2018, 41(1):27-42


The problem of the self-checking built-in checking circuits (concurrent error-detection systems) synthesis by the Boolean complement method of constant-weight codes is investigated. The restrictions on the structure of the components of concurrent error-detection systems are considered by the example of using the “1-out-of-3” code. It is shown that in addition to ensuring the testability of the Boolean complement and the checker in the control circuit, a testable implementation of the object of diagnosis and the check logic block are required. The conditions for ensuring totally self-checking of the concurrent error-detection system structure based on the method of Boolean complement to the “1-out-of-3” code is formulated. Examples illustrating the problem of testing the components and allowing to drawing conclusions about the possibility of using the Boolean complement method in the construction of self-checking discrete systems are given.


self-checking built-in checking circuit, concurrent error-detection system, Boolean complement, the constant-weight codes, «1-out-of-3» code, self-checking structure.


  1. Goessel, M. and Graf, S. (1994), Error Detection Circuits, McGraw Hill, London.
  2. Pradhan, K. (1996), Fault-Tolerant Computer System Design, Prentice Hall, New York.
  3. Bushnell, L. and Agrawal, V.D. (2000), Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VlSI Circuits, Kluwer academic publishers, USA.
  4. Lala, P.K. (2007), Principles of Modern Digital Design, John Wiley & Sons, New-Jersey.
  5. Ubar, , Raik, J. and Vierhaus, H.-T. (2011), Design and Test Technology for Dependable Systems-on-Chip. Information Science Reference, IGI Global, Hershey, New York.
  6. Goessel, , Saposhnikov, Vl., Saposhnikov, V. and Dmitriev, A. (2000), “A New Method for Concurrent Checking by Use of a 1-out-of-4 Code”, 6th IEEE International On-line Testing Workshop, Palma de Mallorca, Spain, July 3-5, 2000, pp. 147-152.
  7. Mitra, and McCluskey, E.J. (2000), “Which Concurrent Error Detection Scheme to Ñhoose?”, International Test Conference, Atlantic City, NJ, USA, October 03-05, 2000, pp. 985-994.
  8. Saposhnikov, V., Saposhnikov, Vl.V. and Morozov, A. (2004), “Design of Totally SelfChecking Combinational Circuits by Use of Complementary Circuits”, East-West Design & Test Workshop, Yalta, Ukraine, 2004, pp. 83-87.
  9. Wang, -T., Wu, C.-W. and Wen, X. (2006), VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann Publishers, San Francisco, USA.
  10. Borecky, , Kohlik, M. and Kubatova, H. (2017), “Parity Driven Reconfigurable Duplex System”, Microprocessors and Microsystems, Vol. 52, pp. 251-260. DOI: 10.1016/j.micpro. 2017.06.015.
  11. Goessel, , Morozov, A.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2005), “Checking Combinational Circuits by the Method of Logic Complement”, Avtomatika i telemekhanika, no. 8, pp. 161-172.
  12. Nicolaidis, and Zorian, Y. (1998), “On-Line Testing for VLSI — A Compendium of Approaches”, Journal of Electronic Testing: Theory and Applications, no. 12, pp. 7-20.
  13. Parkhomenko, P. and Sogomonyan, E.S. (1981), Osnovy tekhnicheskoy diagnostiki (optimizatsiya algoritmov diagnostirovaniya, apparaturnye sredstva) [Basics of technical diagnostics (optimization of diagnostic algorithms and equipment)], Energoatomizdat, Moscow, USSR.
  14. Saposhnikov, V., Morozov, A., Saposhnikov, Vl.V. and Goessel, M. (2002), “Concurrent Checking by Use of Complementary Circuits for «1-out-of-3» Codes”, 5th International Workshop IEEE DDECS, Brno, Czech Republic, April 17-19, 2002.
  15. Goessel, , Morozov, A.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2003), “Logic Complement, a New Method of Checking the Combinational Circuits”, Avtomatika i telemekhanika, no. 1, pp. 167-176.
  16. Go·essel, M., Ocheretny, V., Sogomonyan, E. and Marienfeld, D. (2008), New Methods of Concurrent Checking, Edition 1, Dordrecht: Springer Science+Business Media B.V., Nederland.
  17. Sen, K. (2010), “A Self-Checking Circuit for Concurrent Checking by 1-out-of-4 code with Design Optimization using Constraint Don’t Cares”, National Conference on Emerging trends and advances in Electrical Engineering and Renewable Energy (NCEEERE 2010), Sikkim Manipal Institute of Technology, Sikkim, December 22-24, 2010.
  18. Efanov, , Sapozhnikov, V. and Sapozhnikov, Vl. (2017), “Method of Self-Checking Concurrent Error Detection System Development Based on Constant-Weight Code “2-out-of-4”, Applications and Manufacturing (ICIEAM), Proceeding of 3ed International Conference on Industrial Engineering, St. Petersburg, Russia, May 16-19, 2017, ð. 1-6. DOI: 10.1109/ ICIEAM.2017.8076374.
  19. Sapozhnikov, , Sapozhnikov, Vl. and Efanov, D. (2017), “Combinational Circuit Check by Boolean Complement Method Based on “1-out-of-5” Code”, Proceeding of 15th IEEE East-West Design & Test Symposium (EWDTS’2017), Novi Sad, Serbia, September 29-October 2, 2017, pp. 89-94,
  20. Huches, L.A., McCluskey, E.J. and Lu, D.J. (1984), “Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs”, IEEE Transactions on Computers, Vol. C-33, no. 6, pp. 546-550.
  21. Aksyonova, P. (1979), “Necessary and sufficient conditions for the design of totally checking circuits of compression by modulo 2”, Avtomatika i Telemekhanika, no. 9, pp. 126135.
  22. Das, K., Roy, S.S. and Dmitiriev, A. (2012), “Constraint Don’t Cares for Optimizing Designs for Concurrent Checking by 1-out-of-3 Codes”, Proceeding of the 10th International Workshops on Boolean Problems, Freiberg, Germany, September, 2012, pp. 33-40.
  23. Efanov, , Sapozhnikov, V. and Sapozhnikov, Vl. (2016), “Methods of Organization of Totally Self-Checking Concurrent Error Detection System on the Basis of Constant-Weight «1-out-of-3»-Code”, Proceeding of 14th IEEE East-West Design & Test Symposium (EWDTS’2016), Yerevan, Armenia, October 14-17, 2016, pp. 117-125, DOI: 10.1109/ EWDTS.2016.7807622.
  24. Sapozhnikov, , Sapozhnikov, Vl., and Efanov, D. (2016), “Formation of Totally SelfChecking Structures of Concurrent Error Detection Systems With Use of Constant-Weight Code “1-out-of-3”, Elektronnoe modelirovanie, Vol. 38, no. 6, pp. 25-43.
  25. Sapozhnikov, V., Sapozhnikov, Vl.V. and Efanov, D.V. (2015), “Errors Classification in Information Vectors of Systematic Codes”, Izvestiya Vysshikh Uchebnykh Zavedeniy. Priborostroenie, Vol. 58, no. 5, pp. 333-343.
  26. Sapozhnikov, , Sapozhnikov, Vl., Efanov, D. and Pivovarov, D. (2017), “Synthesis of concurrent error detection systems of multioutput combinational circuits based on Boolean complement method”, Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitelnaya tekhnika i informatika, no. 4, pp. 69-80,
  27. Sogomonyan, E.S. and Go·ssel, M. (1993), “Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs”, Journal of Electronic Testing: Theory and Applications, Vol. 4, Issue 4, pp. 267-281, DOI:10.1007/ BF00971975.
  28. Morosow, , Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Goessel, M. (1998), “SelfChecking Combinational Circuits with Unidirectionally Independent Outputs”, VLSI Design, Vol. 5, Issue 4, p. 333-345,
  29. Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2018), “Synthesis of SelfChecking Combinational Devices Based on Allocating Special Groups of Outputs”, Avtomatika i telemekhanika, no. 9, pp. 79-94.

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